The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed. For example, as semiconductor devices, such as a metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down through various technology nodes, strained source/drain features (stressors) have been implemented using epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Forming a MOSFET with stressor regions often implements epitaxially grown silicon (Si) to form source and drain features for an n-type device, and epitaxially growing silicon germanium (SiGe) to form source and drain features for a p-type device. The epi Si features are often doped with carbon (C) to form Si:C features to further enhance carrier mobility. However, as device technology nodes continue to decrease, it has been observed that (1) traditional epi growth processes limit C solubility in Si epi features (for example, substitutional sites in Si epi are often less than 2%) and (2) incorporating C into the Si epi features tends to deactivate other dopants, such as phosphorous (P) and arsenic (As) (that may be used to form source and drain features, such as heavily doped source and drain features). Accordingly, although existing source/drain stressors and approaches for forming source/drain stressors have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.